Computing devices include many different components which exchange data to perform the operations of the computing device. For example, a memory subsystem typically exchanges data with a central processor, a graphics processor, or others or a combination. A central processor may exchange data with a memory subsystem, a graphics system, multiple peripherals, or others or a combination. Many of the different components operate on different clock speeds, which can means that different devices use different clocks for I/O (input/output) that interconnects to another component. Clock domain crossing refers to the transfer of data from I/O operated with one clock (one clock domain) to I/O operated with a different clock (another clock domain). The misalignment of clock edges can result in setup and hold time violations without proper transfer management. On the other hand, managing the data transfer for setup and hold times can result in latency, especially when transferring from the faster domain to the slower domain as the faster domain may need to wait to transfer on a clock edge that will enable the slower domain to receive the data.
One traditional approach to clock domain transfer is the use of early warning signals associated with the data to transfer. The early warning signal or “valid signal” or valid indicator (referring to a signal that indicates when valid data should be expected at the receiving device) is sent one or more clock cycles prior to the data to allow the receiver to be ready for the data. The management in clock domain crossing can thus include calculation of when to send early warning signals to indicate data. Such calculations are traditionally done based on a ratio of the two clock speeds or a relative offset between the domains.
Traditional approaches to clock domain crossing management do not scale well to high frequency designs. With long clock periods, delays due to clock domain crossings (which may be referred to simply as clock crossings) can significantly affect latency. Such clock crossing issues have been observed when crossing from high speed processors to memory devices. Longer memory latencies have a significant impact on overall system throughput performance as well as power consumption.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.